Substation "Horror Stories" - a Manufacturer's Perspective

Author: Janusz W. Dzieduszko, Quanta Technology, USA

Lesson #5: Do not take anything for granted.

Lesson #5: Do not take anything for granted.

False system operations

Some time following successful installation and integration at the substation, the system described in the previous chapter began to issue false breaker trip commands.

These occurrences were rare (2 to 3 weeks apart), random, and were traced down to all protection clusters. Obviously, much energy, time, and money was invested in attempts to eliminate this unpleasant phenomenon. The complexity of the system opened the door to various theories in two basic areas:

  • Substation noise
  • System software bug

The system passed extensive factory type testing including SWC, Fast Transient, RFI and temperature limits.

Massive utilization of fiber optics for system interfaces eliminated a wide area of suspicion. The system was designed by software and hardware engineers with vast experience in substation requirements.

Software "traps" were added to the system, logic analyzers initialized to trigger on suspected events were installed, and additional filtering and shielding were tried; no answers were obtained. The last element analyzed by the author was Analog Input card in Data Acquisition Unit. (Figure 9)

The microprocessor controlled the A/D conversion process, and using precision REF inputs, provided continuous A/D calibration for temperature and component tolerance drifts.

The calibration was in the form of: Where y - A/D output; a - gain; x - Analog input; b - offset. The A/D had 16-bit output, while the microprocessor was 8049 family 8-bit machine. All arithmetic operations were, therefore, using double precision arithmetic (low byte, high byte).

The assembly language programming was used. Taking the program listings and processor reference manual home, away from the day to day distractions, after several hours of careful instruction by instruction study, the resounding EUREKA! followed.

It was found that doing ax + b addition, the processor checked for possible register overflow (i.e. the result possibly exceeding 15 bit number).

Bit 7 of HIGH BYTE set to "1" indicated that fact, and should result in setting the register to full scale (7FFFhex). Instead of testing that bit, bit 7 of LOW BYTE was tested in error (otherwise known as software "bug").

Full scale input to the A/D was 5 V corresponding to 30 p.u. (150 A rms) for analog inputs. It is easy to compute that the input of approximately 20 mV (0.585 A rms) sets bit 7 of LOW BYTE to a "1", thus causing the false assumption of a huge fault current (equal or greater then 30 p.u.) and subsequent system trip.

Lesson #6: Pay attention to processor architecture. Avoid fixed point arithmetic.

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