High-fidelity HIL modeling on FPGA

The main limitation of HIL simulation on CPU is the time required to transfer data between the I/Os and the CPU that are connected to the Field-Programmable Gate Array (FPGA).
Transfers pass through the PCIe bus, with data transfer times in the microseconds, therefore it wasn't possible to lower the timestep below a few microseconds. By using the FPGA for the same process, OPAL-RT can send data directly to the I/Os without needing to go through the PCIe bus, which enables a faster calculation step.

OPAL-RT pioneered real-time simulation on FPGA and addressed the challenges related to it, making possibilities of tests consequently endless.

Power. Flexible. Easergy.
Let?s start with organization in protection testing